Division and square-root are among the required operations in the IEEE floating point standard. Using the Newton-Ralphson iteration method to compute these functions (Hart et al., "Computer Approximation", New York, John Wiley and Sons, Inc., 1978 edition) does not satisfy the IEEE standard on the accuracy of the final result, even though the iteration has a speed advantage (converges quadratically) over many other algorithms, which often converge linearly. To obtain a correctly rounded number as specified by IEEE, hardware implementations of these two functions are generally done in a linear iterative algorithm, where one or more quotient/root bits are produced in each iteration. Naturally, the algorithm that can produce more and more bits per iteration, and/or can shorten the time to do one iteration, will give a better overall performance, but usually at the expense of more complexity in the implementation. Higher radix non-restoring division (SRT), as explained in a classic paper by Atkins (D. E. Atkins, "Higher-Radix Division Using Estimates of the Divisor and Partial Remainder." IEEE Transactions on Computers, 17, No. 10, October 1968, pp. 925-934), has been the basis of many hardware solutions (The term "radix" refers to the number of different numbers represented by each element. For binary representation, a radix 2 element has one bit, radix 4 has 2 bits, radix 8 has 3 bits, etc.). Radix 8 SRT division has been implemented in a VLSI chip, the Weitek WTL2264 (Weitek Corp., "WTL2264/WTL2265 Floating Point Multiplier/Divider and ALU", data sheet, July 1986). Restoring radix four division shared with radix two square-root has been built and reported by Taylor (G. S. Taylor, "Compatible Hardware for Division and Square Root", Proceedings of the 5th Symposium on Computer Arithmetic, May 1981, pp. 127-134). Non-restoring radix two square-root is described by Majerski (S. Majerski, "Square-rooting Algorithms for High Speed Digital Circuits." IEEE Transactions on Computers, c34, No. 8, August 1985, pp. 724-733).